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NCL30051
VCC
PDRV
UVLO
t PFC(off) Timer
Disable
V ZCD
PDRV
V DD
UVLO
I PFB
VCC
Latch Q
PZCD
PControl
PFB
ZCD
Comparator
+
10V
V DD
Reset
Edge
Detector
> 5.65 V
Clamp
< 2.25 V
Clamp PFC
PFC UVP Error
Amplifier
+
? V PREF
S Q
Dominant
Reset
Latch
R Q
UVLO
V CC
Good
Level
Shifter
I start
+
Management ?
+
?
Undervoltage
Detector
S
Dominant
Reset
R
V CC(on) /
V CC(off) /
UVLO
HV
VCC
C CC
D boost
HBoost
HDRVhi
C boost
HVS
PCT
I PCT(C)
On time
Comparator
Level
Shifter
PFC OVP
Comparator
Pulse
Trigger
Delay
Delay
VCC
HDRVlo
GND
?
V CC Good
V PUVP
V HB(DIS)
3V ?
PCS
LEB
+
PFC UVP
Comparator
+
?
PCS
Comparator
V POVP
Q Q
Clock
Disable
CLK
Q
Q
Enable
?
+
+
?
CLK +
?
+
5 V/
V DD
I OSC(C)
4*I OSC(C)
OSC
+
?
V PCS(ILIM)
PDRV
UVLO
S Q
R
V DD
Voltage
Reference
VREF
Figure 1. Functional Block Diagram
http://onsemi.com
2
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